//*****************************************************************************
//*****************************************************************************
//  FILENAME: speckmac.h
//  Version: 1.0, 
//	Original Author: 	Steven K.J Wong
//						University of Edinburgh
//  Edit by:	
//						Matthew Barnes
//						University of Edinburgh
//
//  DESCRIPTION:
//  Header file SpeckMAC implmentation
//-----------------------------------------------------------------------------
//******************
//Function Declaration
//******************

//Initialize the Duty Cycle Algorithm
void SpeckMAC_Init(void);

//Stop duty-cycling
void SpeckMAC_Stop(void);

void SpeckMAC_Restart(void);

//Tries to send the packet once. Return FAILURE or SUCCESS
//unsigned char SpeckMAC_SendPkt(Packet *pkt);

//Blocks the processor until the packet is sent
void SpeckMAC_SendPktBlocking(Packet *pkt);

//******************
//Parameters for Duty Cycle
//******************
#define LPL_SAMPLEINTERVAL	0.02	//For SpeckMAC_D in seconds (last tested good 0.02)
#define LPL_SAMPLETIMING	(unsigned int) (LPL_SAMPLEINTERVAL * 32768)	//to load to sampling timer

#define LPL_WAKEUPDURATION	(LPL_SAMPLEINTERVAL+0.001)	//in seconds
#define LPL_WAKEUPTIMING	(unsigned int)(LPL_WAKEUPDURATION * 32768)

#define LPL_MAX_IDLE_TIME	0.005	//time channel remains idle and going back to channel sampling 
#define LPL_MAX_IDLE_TIMING	(unsigned int) (LPL_MAX_IDLE_TIME * 32768)

#define LPL_CSMA_CHANNEL_SAMPLE_DURATION	0.001	//the duration to check for channel free. Channel is said to be free if channel is free for the whole duration
#define LPL_CSMA_SAMPLE_DURATION_CLK	(unsigned char)(LPL_CSMA_CHANNEL_SAMPLE_DURATION * 32768)	

//*********************
//Macros for Interrupts
//*********************
#define FIFOP_ENABLE_INT	FIFOP_IntEn_ADDR|=FIFO_MASK
#define FIFOP_DISABLE_INT	FIFOP_IntEn_ADDR&=~FIFO_MASK

#define RxTimer_INT_CLR	INT_CLR1	//DBB0x,DBB1x = INT_CLR1 & DBB2x,DBB3x = INT_CLR2 
#define TxTimer_INT_CLR	INT_CLR1
